1. Field of Art
This disclosure generally relates to the field of electronic design automation (EDA), and more specifically to functional verification of a design.
2. Description of the Related Art
Verification of an electronic circuit design is oftentimes a tedious and time consuming process. As designs get more complex, the likeliness of introducing bugs into a design increases.
Some designs are first implemented using a system-level modeling language written on an interpretive programming language, such as C language or C++ language. After the desired functionality is obtained, the design is implemented in Register Transfer Level using a hardware description language (HDL) such as Verilog or Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL).
The RTL implementation of the design is verified to determine if the design performs the desired functionality. For instance, the RTL implementation may be simulated and the simulation results may be compared to the behavior of the C implementation of the design. If the simulation results of the RTL implementation do not match the simulation results of the C implementation, then the RTL implementation is modified.
As designs get more complex, the likeliness of introducing an error or bug into the RTL implementation increases. As such, when verifying the RTL implementation against the C implementation, the likeliness of finding a mismatch also increases. Furthermore, as the complexity of a design increases, the difficulty in finding the cause of the error and the difficulty in fixing the error increases.
Thus, there is a need for an incremental verification framework of a circuit design to reduce the complexity of finding and fixing errors of an RTL implementation of the design.